1. Field Of The Invention
This invention relates generally to the fabrication of metal-silicon dioxide semiconductor (MOS) devices, and more particularly to the fabrication of self-aligned silicide and lightly doped drain MOS device structures.
2. Description Of The Related Art
Recent developments in MOS fabrication techniques have produced MOS devices in which ever-decreasing device dimensions are realized in order to achieve greater device density and increased operating speeds. This decrease in MOS device dimensions has, however, created a concern over the high sheet resistance in the source/drain regions and hot carrier injection.
That is, as device dimensions continue to decrease, the junction depths of the source/drain regions are reduced so as to minimize parasitic effects. One direct result of this reduction in the source/drain junction depth is an increase of the sheet resistance of the source/drain regions. Another result of decreasing device dimensions bears on the junction integrity when a metal layer is applied to make a contact to the source/drain regions. The shallower the junction, the more difficult it is to reduce the leakage current of the source/drain regions to the substrate.
In order to reduce the sheet resistance of the source/drain regions, a device structure has been developed, known as a self-aligned silicide structure, in which a metal silicide film is formed at the source/drain regions as well as at the polysilicon gate. In a conventional method for fabricating a self-aligned silicide structure, a silicon dioxide side wall spacer is formed before the source/drain and polysilicon regions are silicided. In this conventional process the side wall spacer etch has to clear the source/drain regions that are not intended to be covered by the side wall spacer so that these regions can be silicided. However, since the junctions are already formed, any significant etch into the silicon of the source/drain regions will reduce the junction depth. This is compounded by the fact that during the silicide formation, the top silicon layer of the source/drain regions is consumed by the silicide, thus further reducing the junction depth. As a result, in order to successfully fabricate a self-aligned silicide MOS device by the conventional fabrication process, all the silicon dioxide in the desired silicon region must be cleared without etching significantly into the junctions.
The performance of MOS integrated circuits is also enhanced by decreasing the separation between the source and drain of an MOS transistor, also known as the effective channel length. However, the applied drain-to-source voltage is kept at a constant level irrespective of reductions in channel length which results in a higher electric field being established across the channel region. This elevated electric field has the ability to inject the carriers (electrons or holes) in the channel region across the silicon and silicon dioxide interface and to trap the carriers in the oxide. Since the silicon dioxide layer forms the gate insulator of the MOS device, the trapped charges in the gate oxide have an effect on the electrical characteristics of the device. This is a particular concern from the reliability standpoint since the longer the drain-to-source voltage is applied, the more charges are trapped.
This phenomenon can be alleviated by using a lightly doped drain (LDD) structure in which a lightly doped region is inserted between the channel and the heavily doped source/drain regions. The lightly doped region has the effect of reducing the peak electric field in the channel region, thereby alleviating the hot carrier injection problem. One common way of implementing an LDD structure requires the formation of a side wall spacer, and hence is called a SWS-LDD (side wall spacer lightly doped drain) structure.
The construction of the SWS-LDD device requires the formation of a side wall spacer that is adjacent to the polysilicon gate. This side wall spacer is formed between two ion implantation steps; the first is a light implant, the second is a heavy implant to define the lightly and heavily doped regions, respectively. When the SWS-LDD structure is implemented in CMOS (complementary MOS) technology, two lithographic steps are required for each dopant polarity, one for each of the implants. For the non-LDD structure, only one such lithographic step is required since only one implant is needed.
As a result of the junction integrity problem described above, it has been proposed that the junctions be formed after silicidation, so that the impurities are implanted into or through the silicide. During the subsequent heat treatment, impurities in the silicide diffuse into the silicon to form the junctions. In addition, it is desirable to combine the self-aligned silicide feature with the LDD structure for advanced MOS device applications. When a self-aligned silicide is implemented with an SWS-LDD structure on a CMOS device, one additional lithographic step is required for each dopant polarity to fabricate the device.
In summary, the following three problems or disadvantages are recognized with regard to the fabrication of self-aligned silicide and lightly doped drain MOS structures:
(1) in the implementation of a self-aligned silicide structure, the side wall spacer etching has to be critically controlled; PA1 (2) in the implementation of an SWS-LDD structure in CMOS, an additional lithographic step is required; and PA1 (3) in the implementation of a self-aligned silicide LDD structure in which the junctions are formed after metal deposition or silicide formation, an additional lithographic step is required.